1. Field of the Invention
The present invention relates generally to the field of integrated circuit design and fabrication. In one aspect, the present invention relates to a method and system for simulation and testing of integrated circuits and systems.
2. Description of the Related Art
Integrated circuits are presently tested using a number of structured design-for-testability (DFT) techniques. These techniques rest on the general concept of making all or some state variables (memory elements like flip-flops and latches) directly controllable and observable. If this can be arranged, a circuit can be treated, as far as testing of combinational faults is concerned, as a combinational network. The most-often used DFT methodology is based on scan chains. It assumes that during testing, all (or almost all) memory elements are connected into one or more shift registers. A circuit that has been designed for test has two modes of operation: a normal or functional mode, and a test or scan mode. In the normal mode, the memory elements perform their regular functions. In the scan mode, the memory elements become scan cells that are connected to form a number of shift registers called scan chains. These scan chains are used to shift a set of test patterns into the circuit and to shift out circuit responses, or test responses, to the test patterns. The test responses are then compared to fault-free responses to determine if the circuit works properly. Scan design methodology has gained widespread adoption by virtue of its simple automatic test pattern generation (ATPG) and silicon debugging capabilities. Conventional scan chain testing is performed using pattern-based simulations; however, as the complexity of circuits continues to increase, high fault coverage becomes increasingly difficult with traditional testing paradigms.
While scan chain testing is certainly useful for testing completed integrated circuit devices, the way in which integrated circuits are typically designed—using multiple abstraction levels (such as RTL and Schematic) of the design—creates a need to model test structures at different circuit model abstraction levels and to verify that the different models accurately correspond to one another (i.e., are equivalent). A number of approaches, such as pattern-based simulations, formal and semi-formal verification techniques (e.g., equivalence checking, symbolic simulation, model checking, etc.), are in practice to perform functional equivalency verification. Conventional approaches for verifying the equivalency of circuit models using formal and semi-formal methods typically provide only functional verification, not test verification. When test structures are verified, conventional techniques do so by serially shifting test data patterns of binary data (also referred to as test vectors or scan vectors) into the scan chains models through the scan inputs under the control of a scan clock which essentially represent pattern-based simulations.
As integrated circuits are produced with greater and greater levels of circuit density and complexity, the required testing and verification of the multiple levels of abstraction in circuit representation have become more complex, and traditional techniques for verifying such designs are generally expensive and can incur errors. Therefore, when models for a circuit test structures are maintained at multiple abstraction levels so that different analyses can be performed at the appropriate model level, it is important to be able to verify the equivalency of these representations (e.g. RTL and Schematic or any two) efficiently. Conventional equivalency verification of scan chains using pattern-based simulations is inherently not exhaustive and requires a lot of effort to generate correct patterns. There is also need for careful coverage analysis to ensure reasonable coverage of the design. Thus, efficient verification schemes providing high coverage with minimized effort are needed. Further limitations and disadvantages of conventional systems will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.